1. Field of the Invention
The present invention relates to a semiconductor memory device employing an open bit line architecture, and more particularly, to a semiconductor memory device for reducing a data error due to a distance mismatching.
2. Description of the Related Art
A semiconductor memory device is a device for storing a data into a memory cell and for outputting the data stored from the memory cell. The semiconductor memory device can include a memory core for storing/outputting the data into/from a memory cell and a peripheral device for supporting an interface between the semiconductor memory device and a control unit, such as a central processing unit (CPU).
The memory core structures, which are widely used today, can include a folded bit line architecture and an open bit line architecture. The open bit line architecture is a configuration in which bit line amplification circuits are formed between a bit line pair (BL and BLB), and the folded bit line architecture is a configuration in which the bit line pair (BL and BLB) are formed side by side on one side of the bit line amplification circuits.
In the open bit line architecture, the memory cell is arranged at an intersection where a word line WL crosses a bit line BL. Compared to the folded bit line architecture, the open bit line architecture has a greater density and a reduced cell area.
FIG. 1 is a circuit diagram illustrating a conventional memory core employing an open bit line architecture in a general dynamic random access memory (DRAM) device.
Referring to FIG. 1, the memory core includes a bit line amplification circuit 10, a first column selection transistor 20, a second column selection transistor 30, a first memory cell 40 and a second memory cell 50.
A bit line pair (BL and BLB) is respectively coupled to the first memory cell 40 and the second memory cell 50, and the bit line amplification circuit 10 is coupled between the bit line pair (BL and BLB).
The bit line amplification circuit 10 includes a P-type sense amplifier 12, an N-type sense amplifier 14 and an equalization circuit 16.
The equalization circuit 16 pre-charges the bit line pair (BL and BLB) with a first predetermined voltage VBL.
The P-type sense amplifier 12 charges the bit line pair (BL and BLB) with a second predetermined voltage VCL and the N-type sense amplifier 14 charges the bit line pair (BL and BLB) with a third predetermined voltage VSS.
For example, the first predetermined voltage VBL can be a half of the second predetermined voltage VCL. The second predetermined voltage VCL can be a power voltage and the third predetermined voltage VSS can be a ground voltage.
The column selection transistors 20 and 30 electrically couple the bit line pair (BL and BLB) to local input/output lines (LD and LDB) in response to a column selection signal CSL, respectively. Namely, the first column selection transistor 20 electrically couples the bit line BL to the local input/output line LD in response to the column selection signal CSL, and the second column selection transistor 30 electrically couples the bar bit line BLB to a bar local input/output line LDB in response to the column selection signal CSL.
As illustrated in FIG. 1, the first column selection transistor 20 is arranged in a left side of the bit line amplification circuit 10 and the second column selection transistor 30 is arranged in a right side of the bit line amplification circuit 10.
However, the P-type sense amplifier 12 and the N-type sense amplifier 14 include a much larger transistor than the respective column selection transistors 20 and 30 and occupy a large area of a semiconductor memory device.
Therefore, a distance between the first column selection transistor 20 and the P-type sense amplifier 12 is much longer than that between the second column selection transistor 30 and the P-type sense amplifier 12. Namely, a distance from the local input/output line LD to the P-type sense amplifier 12 is much longer than that from the bar local input/output line LDB to the P-type sense amplifier 12.
As a result, when the data is inputted to or outputted from the memory cells 40 and 50, a data error due to a distance mismatching can occur. That is, because a distance between a memory cell and a respective column selection transistor pair 20 and 30 mismatches, the data error can result.
FIG. 2 is a conventional layout diagram illustrating a memory core in the semiconductor memory device in FIG. 1.
Referring to FIG. 2, the memory core includes an N+ doped layer 1, a gate poly layer 2, a direct contact layer 4, and a bit line poly layer 5. The memory core further includes a bit line amplification circuit 10, column selection transistors TR1 through TR4, and first to sixteenth contacts CON1 through CON16. The memory core employs the open bit line architecture with a first bit line pair BL1 and BL1B and a second bit line pair BL2 and BL2B.
In FIG. 2, a first column selection transistor TR1 and a second column selection transistor TR2 are arranged in a left side of the bit line amplification circuit 10, and a third column selection transistor TR3 and a fourth column selection transistor TR4 are arranged in a right side of the bit line amplification circuit 10.
The first column selection transistor TR1 and the third column selection transistor TR3 electrically couple the first bit line pair BL1 and BL1B to the first local input/output line pair LD1 and LD1B, respectively, in response to the column selection signal CSL. That is, the first column selection transistor TR1 electrically couples the first bit line BL1 to the first local input/output line LD1 in response to the column selection signal CSL and the third column selection transistor TR3 electrically couples the first bar bit line BL1B to the first bar local input/output line LD1B in response to the column selection signal CSL.
The first contact CON1 and the second contact CON2 indicate a source contact of the first column selection transistor TR1, and the third contact CON3 and the fourth contact CON4 indicate a drain contact of the first column selection transistor TR1. The fifth contact CON5 and the sixth contact CON6 indicate a source contact of the second column selection transistor TR2, and the seventh contact CON7 and the eighth contact CON8 indicate a drain contact of the second column selection transistor TR2. The ninth contact CON9 and the tenth contact CON10 indicate a source contact of the third column selection transistor TR3, and the eleventh contact CON11 and the twelfth contact CON12 indicate a drain contact of the third column selection transistor TR3. The thirteenth contact CON13 and the fourteenth contact CON14 indicate a source contact of the fourth column selection transistor TR4, and the fifteenth contact CON15 and the sixteenth contact CON16 indicate a drain contact of the fourth column selection transistor TR4.
A cell pitch can be defined as a distance between the drain of the first column selection transistor TR1 and the drain of the second column selection transistor TR2. In FIG. 2, the first and second bit line pairs BL1 and BL1B, and BL2 and BL2B can not be arranged within the cell pitch. Therefore, the distance between the first column selection transistor TR1 and the bit line amplification circuit, and the distance between the third column selection transistor TR3 and the bit line amplification circuit 10 are not equivalent to each other.
For example, the distance between the first column selection transistor TR1 and the bit line amplification circuit 10 coupled to the first bit line BL1 can be greater than that between the third column selection transistor TR3 and the bit line amplification circuit 10 coupled to the first bar bit line BL1B. As a result, the data error can occur because a distance between a memory cell and a respective column selection transistor pair TR1 and TR3 mismatches.